네모난 세상
[OS] DMA 본문
Direct Memory Access
하드디스크 드라이브 같은 많은 용량의 데이터 전송이 있을 때, CPU개입 없이 DEVICE에서 바로 메모리로 데이터를 보내는 것을 의미한다. (블록 단위로)
디스크 컨트롤러, 그래픽 카드, 네트워크 카드 및 사운드 카드를 포함한 많은 하드웨어 시스템들은 DMA를 사용한다. DMA 채널을 가진 컴퓨터는 그렇지 않은 컴퓨터보다 CPU 오버헤드를 줄이고 장치와의 데이터 전송을 할 수 있다.
DMA 컨트롤러는 입출력 작업 완료시 CPU에게 인터럽트로 알려준다.
DMA는 개념적으로 데이터 레지스터를 가질 필요가 없다.
DMA는 IBM의 특허기술이었다. (현재는 특허권 소멸)
문제)
1.1 In a multiprogramming and time-sharing environment, several users share the system simultaneously. This situation can result in various security problems.
a. What are two such problems?
->
Stealing or copying one’s programs or data; using system resources
(CPU, memory, disk space, peripherals) without proper
accounting.
b. Can we ensure the same degree of security in a time-shared machine as in a dedicated machine? Explain your answer.
->
Probably not, since any protection scheme devised by humans
can inevitably be broken by a human, and the more complex
the scheme, the more difficult it is to feel confident of its correct
implementation.
1.7 What is the purpose of interrupts? What are the differences between a trap and an interrupt? Can traps be generated intentionally by a user program? If so, for what purpose?
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An interrupt is a hardware-generated change-of-flow within
the system. An interrupt handler is summoned to deal with the cause
of the interrupt; control is then returned to the interrupted context and
instruction. A trap is a software-generated interrupt. An interrupt can
be used to signal the completion of an I/O to obviate the need for device
polling. A trap can be used to call operating system routines or to catch
arithmetic errors.
1.8 Direct memory access is used for high-speed I/O devices in order to avoid increasing the CPU's execution load.
a. How does the CPU interface with the device to coordinate the transfer?
b. How does the CPU know when the memory opreations are complete?
c. The CPU is allowed to execute other programs while the DMA controller is transferring data. Does this process interfere with the execution of the user programs? If so, describe what forms of interference are caused.
->
The CPU can initiate a DMA operation by writing values
into special registers that can be independently accessed by the device.
The device initiates the corresponding operation once it receives a command
from the CPU. When the device is finished with its operation, it
interrupts the CPU to indicate the completion of the operation.
Both the device and the CPU can be accessing memory simultaneously.
The memory controller provides access to the memory bus in a fair
manner to these two entities. A CPU might therefore be unable to issue
memory operations at peak speeds since it has to compete with the
device in order to obtain access to the memory bus.
